The size and performance of DRAM (Dynamic Random Access Memory) memory cells substantially depend on leakage currents of a memory cell comprising a selector transistor and a storage capacitor. The leakage currents of the storage capacitor decrease an electrical charge that characterizes a data content in the storage capacitor. After a time interval dependent on the magnitude of the leakage currents, the stored electrical charge in the storage capacitor is reduced to an extent such that the storage capacitor must be charged again in order to preserve the data content. This time interval is also referred to as the retention time, a short retention time signifying frequent recharging of the storage capacitor. The more frequently the storage capacitors have to be recharged, the more energy is consumed. Moreover, frequent recharging delays access times to data contents. Therefore, it is desirable to keep the retention time as long as possible.
The retention time is proportionally dependent on the storage capacitance of the storage capacitor and inversely dependent on the magnitude of the leakage currents. Thus, the higher the storage capacitance of the storage capacitor, the longer the retention time, and the higher the leakage currents that occur, the shorter the retention time. Since an increase in the storage capacitance of the storage capacitor is usually accompanied by an enlargement of an overall size of the memory cell, it is desirable to reduce the leakage currents that occur in the memory cell.
In vertical memory cells, the storage capacitor is formed in a deep trench in a semiconductor substrate. The selection transistor is oriented vertically with respect to the substrate surface and arranged essentially between the substrate surface and the storage capacitor. The connection of the storage capacitor to the selection transistor is formed by an outdiffusion of dopant from a polysilicon that forms an inner electrode of the storage capacitor. The outdiffusion results in a lower source/drain region of the selection transistor. In the case of a DRAM memory comprising vertical memory cells, the individual memory cells are arranged next to one another in rows. Adjacent rows are separated from one another in each case by an active trench. The active trenches are in each case to be provided with a depth such that lower source/drain regions of memory cells of adjacent rows are electrically isolated from one another. Gate electrodes assigned to the selection transistors are in each case formed at least in segments in the active trenches, the gate electrodes of adjacent selection transistors in a row adjoining one another and forming addressing lines. In this case, the addressing lines are provided in the active trenches, in a known manner, as spacer structures situated on a bottom of the active trenches. Since the active trenches extend to below an upper edge of the inner electrodes, there is an overlap between segments of the gate electrode, or the addressing lines, and the inner electrode of the storage capacitor. Such an overlap results in a disadvantageous leakage current from the storage capacitor.
A further leakage current is induced by the gate electrode in a switched-off state of a selection transistor. This leakage effect is also referred to as the GIDL effect (Gate Induced Drain Leakage). The GIDL effect is based on a strong band bending—occurring in the switched-off state of the selection transistor—in an overlap region between the gate electrode and the source/drain region. The GIDL effect and thus the magnitude of the leakage current can be reduced by reducing a source/drain overlap region between the gate electrode and the highly doped lower source/drain region.